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DIVIDER FAULT DETECTION CIRCUIT AND DIVIDER FAULT DETECTION METHOD USED FOR THE SAME

机译:除法故障检测电路和用于同一方法的除法故障检测方法

摘要

PROBLEM TO BE SOLVED: To provide a divider fault detection circuit capable of reducing a hardware amount for division check and checking the entire divider.;SOLUTION: A modulo 3 result 204 generated in a modulo 3 generation circuit 11 of a quotient from a rounding processing result by a rounding circuit 12 and a rounding addition circuit 13, and the module 3 result 202 of a divisor obtained in the modulo 3 generation circuit 4 for the divisor are multiplied in the modulo 3 generation circuit 5 of a product, and the result and the modulo 3 result 203 of a partial remainder obtained in a partial remainder modulo 3 generation circuit 14 are added in the modulo 3 generation circuit 6 of a sum. An added modulo 3 result 206 is compared with the modulo 3 result 201 of a dividend generated beforehand in the modulo 3 generation circuit 3 for the dividend in a comparator circuit 7, and whether or not a fault is present in a quotient generation part 10, the rounding circuit 12 and the rounding addition circuit 13 is judged.;COPYRIGHT: (C)2003,JPO
机译:要解决的问题:提供一种除法器故障检测电路,该电路能够减少用于除法检查和检查整个除法器的硬件量;解决方案:在模3生成电路11中根据舍入处理生成的模3结果204由舍入电路12和舍入加法电路13得到的结果,将在模3生成电路4中获得的除数的模块3的结果202的乘数在乘积的模3生成电路5中相乘。在部分余数模3生成电路14中获得的部分余数的模3结果203被加到和3的模3生成电路6中。将相加后的模3结果206与在模3生成电路3中预先生成的除数的模3结果201进行比较,以用于比较器电路7中的除数,并且在商生成部10中是否存在故障,判断舍入电路12和舍入加法电路13。版权所有:(C)2003,日本特许厅

著录项

  • 公开/公告号JP2002342071A

    专利类型

  • 公开/公告日2002-11-29

    原文格式PDF

  • 申请/专利权人 NEC COMPUTERTECHNO LTD;

    申请/专利号JP20010145732

  • 发明设计人 UESUGI TAKAHIKO;

    申请日2001-05-16

  • 分类号G06F7/52;

  • 国家 JP

  • 入库时间 2022-08-22 00:13:30

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