Apparatus and method for improved execution of a software pipeline loop procedure in a digital signal processor

摘要

A program memory controller unit includes apparatus for the execution of a software pipeline procedure in response to a predetermined instruction. The apparatus provides a prolog state, a kernel state, and an epilog state for the execution of the software pipeline procedure. In addition, in response to a predetermined condition, the software pipeline loop procedure can be terminated early. Apparatus is provided whereby a second software pipeline loop procedure can be initiated prior to the completion of a first software pipeline procedure. Two additional instructions are provided for addressing problems resulting from hardware pipeline delays and for more efficient program execution.