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Hard mask trimming with thin hard mask layer and top protection layer

机译:用薄的硬掩模层和顶部保护层修整硬掩模

摘要

Hard mask trimming with a thin hard mask layer and a top protection layer is disclosed. During fabrication of a semiconductor device, the device has a primary layer, a lower layer, and an upper layer. The primary layer, which may be a polysilicon layer, has a critical dimension specification. The lower layer is over the polysilicon layer, and is subsequently hard mask trimmed to satisfy the critical dimension specification of the primary layer. The upper layer is over the lower layer, and has a high-etching selectivity as compared to the lower layer. The upper layer substantially prevents thickness loss of the lower layer during hard mask trimming. Each of the upper layer and the lower layer may be Si3N4, SiON, or SiO2. Additionally, the upper layer may be polysilicon.
机译:公开了具有薄的硬掩模层和顶部保护层的硬掩模修整。在半导体器件的制造期间,该器件具有主层,下层和上层。可以是多晶硅层的主要层具有临界尺寸规格。下层在多晶硅层上,然后进行硬掩模修整,以满足基本层的关键尺寸规格。上层在下层之上,并且与下层相比具有高蚀刻选择性。上层基本上防止了在硬掩模修整期间下层的厚度损失。上层和下层的每一个可以是Si 3 N 4 ,SiON或SiO 2 。另外,上层可以是多晶硅。

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