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Booster circuit for raising voltage by sequentially transferring charges from input terminals of booster units to output terminals thereof in response to clock signals having different phases

机译:升压电路,用于通过响应于具有不同相位的时钟信号,将电荷从升压单元的输入端子顺序转移到升压单元的输出端子来升高电压

摘要

A booster circuit includes a plurality of booster units whose output terminals are respectively connected to the input terminals of the next-stage booster units, and an output circuit section. Each of the booster units sequentially transfers charges from the input terminal to the output terminal in response to clock signals to raise a positive or negative voltage input to a first-stage booster unit. Then, a node in which charges are left behind is reset by use of a reset signal after the charge transfer. The potential of the reset signal for turning ON the resetting transistor is created from the positive or negative boosted potential output from the output circuit section.
机译:升压电路包括:多个升压单元,其输出端子分别连接至下一级升压单元的输入端子;以及输出电路部。每个升压单元响应于时钟信号而将电荷从输入端子顺序转移到输出端子,以升高输入到第一级升压单元的正电压或负电压。然后,在电荷转移之后通过使用复位信号来复位其中留下电荷的节点。从输出电路部分输出的正或负升压电位产生用于使复位晶体管导通的复位信号的电位。

著录项

  • 公开/公告号US2002196673A1

    专利类型

  • 公开/公告日2002-12-26

    原文格式PDF

  • 申请/专利权人 KABUSHIKI KAISHA TOSHIBA;

    申请/专利号US20020212062

  • 发明设计人 TORU TANZAWA;

    申请日2002-08-06

  • 分类号G11C7/00;

  • 国家 US

  • 入库时间 2022-08-22 00:09:13

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