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System and method for improving dram single cell fail fixability and flexibility repair at module level and universal laser fuse/anti-fuse latch therefor
System and method for improving dram single cell fail fixability and flexibility repair at module level and universal laser fuse/anti-fuse latch therefor
A universal fuse latch device comprises a latch circuit receiving a precharge signal and latching the precharge signal at a latch node thereof for initializing the latch to a first state; and one or more legs connected at the latch node, with a first leg implementing a fuse type element capable of transitioning the latch from the first state to a second state, and a second leg including an anti-fuse type element, wherein the fuse latch is provided with a fuse resistance trip point to ensure adequate programming of one of the fuse and anti-fuse type element. In one application, the universal fuse latch device is implemented as part of a programmable fuse bank comprising a plurality of information fuse latches for storing redundancy information in a memory system and capable of being simultaneously interrogated. A master fuse control device comprising the universal fuse latch circuit is provided that is programmed in accordance with a priority of legs to be interrogated in the information fuse latches. The system and method of the invention implements logic circuits and devices for determining the priority of legs that are to be interrogated for accessing the redundancy information and for generating appropriate interrogation strobe and leg selection signals to enable proper interrogation of the information fuse latches according to the determined priority.
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