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Mosfet having a variable gate oxide thickness and a variable gate work function, and a method for making the same

机译:具有可变的栅极氧化物厚度和可变的栅极功函数的mosfet及其制造方法

摘要

A transistor has a gate with a variable work function and a gate oxide layer with variable thickness. The gate oxide layer has an area of reduced thickness at its center, and the gate is made from central and peripheral portions. The central portion is formed over the central (thinner) portion of the gate oxide layer, and the peripheral portions are formed over the thicker areas of the gate oxide layer. The gate, gate oxide layer, and two source/drain regions may be formed in a damascene trench for improved performance, and lightly doped drain (LDD) regions preferably extend from the source/drain regions in overlapping relationship with the peripheral portions of the gate. Additionally, a method for making an asymmetrical transistor is presented, which involves applying a gate oxide layer on a semiconductor layer in contact with a sidewall structure. A first spacer made of a gate material is formed on the structure and gate oxide layer. An LDD region is then formed in the semiconductor layer, using the first spacer as a mask for alignment purposes. This is followed by formation of a second spacer on the gate oxide layer in overlapping relationship with the LDD region. The second spacer contacts the first spacer and is made of a gate material, and thus the first and second spacers collectively form the gate of the transistor. Final processing steps are performed to finish the device.
机译:晶体管具有具有可变功函数的栅极和具有可变厚度的栅极氧化物层。栅极氧化物层在其中央具有减小的厚度的区域,并且栅极由中央和外围部分制成。中央部分形成在栅极氧化物层的中央(较薄)部分上,而外围部分形成在栅极氧化物层的较厚区域上。可以在镶嵌沟槽中形成栅极,栅极氧化物层和两个源极/漏极区域以提高性能,并且轻掺杂漏极(LDD)区域优选地以与栅极的外围部分重叠的关系从源极/漏极区域延伸。 。另外,提出了一种用于制造不对称晶体管的方法,该方法包括在与侧壁结构接触的半导体层上施加栅极氧化物层。由栅极材料制成的第一间隔物形成在结构和栅极氧化物层上。然后,使用第一间隔物作为用于对准目的的掩模,在半导体层中形成LDD区域。随后在与LDD区域重叠的关系的栅氧化层上形成第二隔离物。第二隔离物接触第一隔离物并且由栅极材料制成,因此第一隔离物和第二隔离物共同形成晶体管的栅极。执行最终处理步骤以完成设备。

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