首页> 外国专利> Differential signal output apparatus, semiconductor integrated circuit apparatus having the differential signal output apparatus, differential signal transmission system, signal detection apparatus, signal detection method, signal transmission system and computer-readable program

Differential signal output apparatus, semiconductor integrated circuit apparatus having the differential signal output apparatus, differential signal transmission system, signal detection apparatus, signal detection method, signal transmission system and computer-readable program

机译:差分信号输出设备,具有该差分信号输出设备的半导体集成电路设备,差分信号传输系统,信号检测设备,信号检测方法,信号传输系统和计算机可读程序

摘要

In a differential output signal circuit suitable for restraining voltage overshooting/undershooting at differential output terminals due to lags in input signals and realizing stable and fast switching of differential input signals, a first differential pair of PMOS transistors connected to a first current source and a second differential pair of NMOS transistors connected to a second current source are mutually connected at the differential output terminals, and a capacitor is connected between the connection nodes of the respective differential pairs and current sources. A transitional current path of the capacitor restrains voltage variations during differential input signal switching. Further in a signal detection apparatus suitable for realizing the detection of fast transmitted differential input signals with less current consumption and at low cost, an edge detect signal is supplied against a differential input of or above a prescribed value, and a setting signal is issued when this edge detect signal has been detected a prescribed number of times during a first prescribed length of time while a resetting signal is issued if none is detected during a second prescribed length of time. A signal-detect signal is generated from these setting signal and resetting signal.
机译:在适于抑制由于输入信号的滞后引起的差分输出端子上的电压过冲/下冲并且实现差分输入信号的稳定和快速切换的差分输出信号电路中,第一PMOS差分对对连接到第一电流源和第二PMOS晶体管对。连接到第二电流源的NMOS晶体管的差分对在差分输出端子处相互连接,并且电容器连接在各个差分对的连接节点和电流源之间。电容器的过渡电流路径可抑制差分输入信号切换期间的电压变化。此外,在适合于以较少的电流消耗和低成本实现对快速传输的差分输入信号的检测的信号检测装置中,针对等于或大于规定值的差分输入提供边缘检测信号,并且当以下情况时发出设置信号:如果在第二规定时间长度内没有检测到复位信号,则在第一规定时间长度内已经检测到该边缘检测信号规定次数,而发出复位信号。从这些设置信号和复位信号产生信号检测信号。

著录项

  • 公开/公告号US2003001666A1

    专利类型

  • 公开/公告日2003-01-02

    原文格式PDF

  • 申请/专利权人 FUJITSU LIMITED;

    申请/专利号US20010973767

  • 发明设计人 HIDEAKI WATANABE;HIROKO HARAGUCHI;

    申请日2001-10-11

  • 分类号G06G7/12;

  • 国家 US

  • 入库时间 2022-08-22 00:08:33

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