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Method of forming S/D extension regions and pocket regions based on formulated relationship between design and measured values of gate length
Method of forming S/D extension regions and pocket regions based on formulated relationship between design and measured values of gate length
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机译:基于设计和浇口长度测量值之间的公式化关系形成S / D延伸区和袋状区的方法
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摘要
The relationship between the difference between design and measured values of the gate length of a gate electrode of a transistor and the dose of an impurity to be injected into SD extension regions or pocket regions which is necessary to equalize characteristics of the transistor to design values is formulated. The gate length of the gate electrode which is produced by photolithography and etching process is measured. The dose of the impurity to be injected into the SD extension regions or the pocket regions is adjusted to bring deviations of the characteristics of the transistor from the design values into a predetermined range, based on the measured value of the gate length and the formulated relationship.
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