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Evaluation device of weighted fault coverage and evaluation method of the same

机译:加权故障覆盖率评估装置及其评估方法

摘要

The present invention provides evaluation device and evaluation method of weighted fault coverage useful for creation of test patterns of high fault coverage corresponding to manufacturing quality of LSI at high precision. In the evaluation device and evaluation method of fault coverage of the present invention, in a large scale integration such as system LSI, in order to utilize the results of fault simulation or ATPG in improvement of quality in the manufacturing field, the faults assumed in logic connection nodes and input and output terminals of the internal basic cell are weighted in relation to various data relating to fault occurrence extracted from the actual layout data, and the weighted fault coverage is calculated from the result of fault simulation or ATPG by using them. Accordingly, at an early stage of a manufacturing process, the fault coverage for faults of high occurrence is obtained with high precision, and by adding the test patterns so as to enhance the weighted fault coverage, the manufacturing quality of LSI can be enhanced efficiently.
机译:本发明提供了加权故障覆盖率的评估装置和评估方法,该评估设备和加权故障覆盖率的评估方法可用于创建与高精度的LSI的制造质量相对应的高故障覆盖率的测试图案。在本发明的故障覆盖率的评估装置和评估方法中,在大规模集成中,例如系统LSI,为了利用故障模拟或ATPG的结果来提高制造领域的质量,逻辑上假设了故障相对于从实际布局数据中提取的与故障发生相关的各种数据,对内部基本单元的连接节点以及输入和输出端子进行加权,并使用故障模拟或ATPG的结果计算加权的故障覆盖率。因此,在制造过程的早期阶段,可以高精度地获得针对高发生率的故障的故障覆盖率,并且通过添加测试图案以增强加权的故障覆盖率,可以有效地提高LSI的制造质量。

著录项

  • 公开/公告号US6567946B1

    专利类型

  • 公开/公告日2003-05-20

    原文格式PDF

  • 申请/专利权人 KABUSHIKI KAISHA TOSHIBA;

    申请/专利号US20000532882

  • 发明设计人 YASUYUKI NOZUYAMA;

    申请日2000-03-22

  • 分类号G06F110/00;

  • 国家 US

  • 入库时间 2022-08-22 00:06:52

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