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Incorporation of split-adder logic within a carry-skip adder without additional propagation delay
Incorporation of split-adder logic within a carry-skip adder without additional propagation delay
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机译:在进位跳过加法器中合并了分频加法器逻辑,而没有额外的传播延迟
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摘要
An n-bit carry-skip adder includes a number of carry-skip stages and a logic circuit associated with one or more of the stages. The logic circuit includes split-adder logic and carry-skip logic configured such that a split control signal associated with the split-adder logic is applied to at least one gate of the carry-skip logic, so as to reduce a carry propagation delay of the adder. In an illustrative embodiment, the logic circuit is associated with an (n/2+1)th carry-skip stage of the adder, and the adder is configured to perform two parallel n/2-bit additions when the split control signal is at a first logic level, and to perform a single n-bit addition when the split control signal is at a second logic level. Advantageously, the invention allows the split-adder logic to be incorporated in a manner which minimizes the carry propagation delay without increasing the required circuit area.
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机译: 转换术语± Sup> [n i Sub>] f(+/-) min sup>的条件最小化结构的逻辑动态过程的方法Sub> AND ± Sup> [m i Sub>] f(+/-) min Sub>在功能添加结构中± Sup> f < Sub> 1 Sub>(Σ RU Sub>) min Sub>,不带纹波f 1 Sub>(± Sup>←←)和循环ΔtΣ Sub>→5∙f(&)-和5个条件逻辑函数f(&)-,并通过三元数系统的算术公理同时转换术语参数的过程f RU Sub>(+ 1,0,-1)及其实现其的功能结构(俄罗斯逻辑版本)