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Cascading PLL units for achieving rapid synchronization between digital communications systems
Cascading PLL units for achieving rapid synchronization between digital communications systems
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机译:级联PLL单元以实现数字通信系统之间的快速同步
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摘要
A clock synchronization system for synchronizing a first communications device and a second communications device to enable digital communication there between. A first device generates a first clock signal Fa. A second device generates a second clock signal Fb2. The second device includes a first PLL circuit and a second PLL circuit. The first PLL circuit is adapted to increase Fa by a factor K to produce a signal Fak. The second PLL circuit is adapted to increase Fak by a factor L to produce a signal Fbn. The second PLL circuit is further adapted to decrease Fbn by a factor N to produce the signal Fb2. The first PLL circuit and the second PLL circuit are adapted to adjust the values of K, L, and N such that a frequency lock is achieved between Fa and Fb2. enabling digital communication between the first device and the second device without requiring a predetermined phase lock between Fa and Fb2. 展开▼