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System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing
System for handling coherence protocol races in a scalable shared memory system based on chip multiprocessing
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机译:基于芯片多处理的可伸缩共享存储系统中处理一致性协议竞赛的系统
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摘要
In a chip multiprocessor system, the coherence protocol is split into two cooperating protocols implemented by different hardware modules. One protocol is responsible for cache coherence management within the chip, and is implemented by a second-level cache controller. The other protocol is responsible for cache coherence management across chip multiprocessor nodes, and is implemented by separate cache coherence protocol engines. The cache controller and the protocol engine within each node communicate and synchronize memory transactions involving multiple nodes to maintain cache coherence within and across the nodes. The present invention addresses race conditions that arise during this communication and synchronization.
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