Approach to structurally reinforcing the mechanical performance of silicon level interconnect layers

摘要

A conductive via pattern (110) between the uppermost metal interconnect layer (M_n) and next underlying metal interconnect layer (M_n−1) in the bond pad areas strengthens the interlevel dielectric (ILD3) between metal layers (M_n and M_n−1). The conductive via layer (110) may, for example, comprise parallel rails (114) or a grid of cross-hatch rails (116). By spreading the stress concentration laterally, the conductive via layer (110) inhibits micro-cracking from stress applied to the bond pad (112).