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High speed lock acquisition mechanism with time parameterized cache coherency states
High speed lock acquisition mechanism with time parameterized cache coherency states
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机译:具有时间参数化的缓存一致性状态的高速锁获取机制
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摘要
A multiprocessor data processing system requires careful management to maintain cache coherency. In conventional systems using a MESI approach, two or more processors will often compete for ownership of a common cache line. As a result, ownership of the cache line will frequently “bounce” between multiple processors, which causes a significant reduction in cache efficiency. The preferred embodiment provides a modified MESI state which holds the status of the cache line static for a fixed period of time, which eliminates the bounce effect from contention between multiple processors.
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