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External direct memory access processor implementation that includes a plurality of priority levels stored in request queue
External direct memory access processor implementation that includes a plurality of priority levels stored in request queue
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机译:外部直接存储器访问处理器实现,包括存储在请求队列中的多个优先级
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摘要
An external direct memory access unit includes an event recognizer storing plural event types in an event register, a priority encoder selecting for service one recognized external event, a parameter memory storing service request parameters corresponding to each event type and an external direct memory access controller recalling service request parameters from the parameter memory corresponding to recognized events and submitting them to a centralized direct memory access unit. The external direct memory access controller may update source or destination address for a next occurrence of an event type by adding an offset or updating an address pointer to a linked list. The centralized direct memory access unit queues data transfer parameters on a priority channel basis and stalls the external direct memory access controller for a particular priority level it the corresponding queue is full. The use of a report word or an alternate report word signals the centralized direct memory access unit to prohibit or permit interruption of an executing data transfer. An event mask permits selective masking of event types. A central processing unit may trigger an external event by writing to a corresponding bit in the event register.
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