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Address generation unit and digital signal processor (DSP) including a digital addressing unit for performing selected addressing operations
Address generation unit and digital signal processor (DSP) including a digital addressing unit for performing selected addressing operations
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机译:地址生成单元和包括用于执行选定的寻址操作的数字寻址单元的数字信号处理器(DSP)
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摘要
An address generation unit (AGU) and a digital signal processor (DSP) including such an AGU are disclosed. The AGU (3) has a register file (4) providing order (R), stage (S), and displacement (N) values to a digital addressing unit (DAU) (5) for performing one of eight addressing operations. The register file provides an input (X) to the DAU and receives an output (Y) from the DAU. Within the DAU (5), selection multiplexers (13, 14) select full adder outputs to provide Y, or bit-select from adders and the input (X) to provide Y. For a radix-4 operation, most significant bits (MSBs) are taken from the input (X), middle bits are taken from the output of a first adder (adder1), and the least significant bits (LSBs) are taken from the output of a second adder (adder2) if there is a carry out from the first adder. The AGU may also include bit reverse blocks connected at both the input and output of an adder. The DSP includes a program control unit for delivering a control signal to the AGU for selection of a required addressing operation.
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