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Dyadic DSP instruction processor with main and sub-operation functional blocks selected from each set of multiplier and adder
Dyadic DSP instruction processor with main and sub-operation functional blocks selected from each set of multiplier and adder
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机译:Dyadic DSP指令处理器,具有从每组乘法器和加法器中选择的主要和子操作功能块
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摘要
A dyadic digital signal processing (DSP) instruction processor including a first DSP functional block to execute a main operation of a dyadic DSP instruction and a second DSP functional block to execute a sub operation of the dyadic DSP instruction with data paths of each selectively configured to execute the main operation and the sub operation of the dyadic DSP instruction. A voice and data communication system has a first gateway and a second gateway coupled to a packetized network, each gateway having a network interface including the dyadic DSP instruction processor. An application specific signal processor with a signal processor having a first DSP functional block to execute a main operation of a dyadic DSP instruction and a second DSP functional block to execute a sub operation with multiplexers coupled to the first DSP functional block and the second DSP functional block to selectively configure data paths thereto.
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