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Circuit arrangement for generating a clock-pulse signal having a frequency synchronous with a reference clock-pulse signal
Circuit arrangement for generating a clock-pulse signal having a frequency synchronous with a reference clock-pulse signal
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机译:用于产生具有与参考时钟脉冲信号同步的频率的时钟脉冲信号的电路装置
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摘要
To synchronize a controllable oscillator with a first reference clock signal, a first phase locked loop having a first phase comparison device is provided. In addition, the synchronous-frequency clock signal from the oscillator is supplied to a second phase comparison device for phase comparison with a second reference clock signal via an inventive phase control element for inserting and removing clock phases. On the basis of the output signal from the second phase comparison device, phase correction information is formed and on the basis of this phase correction information the insertion and removal of clock phases is controlled in the phase control element. If the first reference clock signal disappears, the oscillator is stabilized using the second reference clock signal by taking into account the phase correction information formed previously.
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