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Circuit arrangement for generating a clock-pulse signal having a frequency synchronous with a reference clock-pulse signal

机译:用于产生具有与参考时钟脉冲信号同步的频率的时钟脉冲信号的电路装置

摘要

To synchronize a controllable oscillator with a first reference clock signal, a first phase locked loop having a first phase comparison device is provided. In addition, the synchronous-frequency clock signal from the oscillator is supplied to a second phase comparison device for phase comparison with a second reference clock signal via an inventive phase control element for inserting and removing clock phases. On the basis of the output signal from the second phase comparison device, phase correction information is formed and on the basis of this phase correction information the insertion and removal of clock phases is controlled in the phase control element. If the first reference clock signal disappears, the oscillator is stabilized using the second reference clock signal by taking into account the phase correction information formed previously.
机译:为了使可控振荡器与第一参考时钟信号同步,提供了具有第一相位比较装置的第一锁相环。另外,来自振荡器的同步频率时钟信号经由本发明的用于插入和去除时钟相位的相位控制元件被提供给第二相位比较装置,用于与第二参考时钟信号进行相位比较。基于来自第二相位比较装置的输出信号,形成相位校正信息,并且基于该相位校正信息,在相位控制元件中控制时钟相位的插入和去除。如果第一参考时钟信号消失,则通过考虑先前形成的相位校正信息,使用第二参考时钟信号使振荡器稳定。

著录项

  • 公开/公告号US6559696B1

    专利类型

  • 公开/公告日2003-05-06

    原文格式PDF

  • 申请/专利权人 SIEMENS AKTIENGESELLSCHAFT;

    申请/专利号US20020089180

  • 发明设计人 JUERGEN HEITMANN;EDUARD ZWACK;

    申请日2002-03-27

  • 分类号H03L70/60;

  • 国家 US

  • 入库时间 2022-08-22 00:04:25

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