Method and device for addressable failure site test structure

摘要

A test structure for detecting defects in a semiconductor wafer and a method for using such test structure are provided. The test structure includes conduction units arranged in an array and test pads connecting to the conduction units. A conduction unit includes closely spaced or intermeshed conduction paths. The test pads are divided into X and Y groups. A pair of test pads X(i), X(i+1) are set to high voltage, a pair of test pads Y(j), Y(j+1) are set to low voltage, and the other test pads are floated. The current I(i, j) flowing from test pad pairs X to Y is measured. If current I(i, j) is a local minimum, then conduction unit (i, j) has a short circuit defect.