A minimal level sensitive timing abstraction model supports multiple levels of hierarchy, is input stimulus independent, can be input into general static timing analysis (STA) tools, and limits timing analysis to the most critical paths, i.e., the most critical arrival at any given port, leading to significant reduction of the number of internal clock-controlled nodes, which in turn results in significant speed-up of STA runs on large circuits and reduced memory and storage space requirements. Further speed-up of STA runs may be achieved by tracing only the most relevant transparent paths to a given output port, which reduces the number of paths fed to the adjacent blocks. The timing abstraction model may also simplify the output from the timing analysis and may shorten designer's time to analyze STA results.
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