Method and system for resolution of transaction collisions to achieve global coherence in a distributed symmetric multiprocessor system

摘要

A distributed system structure for a large-way, symmetric multiprocessor system using a bus-based cache-coherence protocol is provided. The distributed system structure contains an address switch, multiple memory subsystems, and multiple master devices, either processors, I/O agents, or coherent memory adapters, organized into a set of nodes supported by a node controller. The node controller receives commands from a master device, communicates with a master device as another master device or as a slave device, and queues commands received from a master device. The node controller has a deterministic delay between latching a snooped command broadcast by the address switch and presenting the command to the master devices on the node controller's master device buses. Since the achievement of coherency is distributed in time and space, the node controller helps to maintain cache coherency for commands by contributing one or more inputs into a determination of a coherency response for commands based on the types of commands and the phases of commands queued within the node controller. A response combination block logically combines, generates, and then transmits command status signals and command response signals associated with commands issued by master devices. The system is able to achieve the correct order of complete for transactions using these coherency inputs.