COMBINED INTERLEAVER AND DEINTERLEAVER, AND TURBO DECODER COMPRISING A COMBINED INTERLEAVER AND DEINTERLEAVER

摘要

A combined interleaving and deinterleaving circuit (IDL1) comprises a first data memory (RAM) for temporarily storing the data to be interleaved or deinterleaved. A first address generator generates a sequence of consecutive addresses and a second address generator (AG) generates a sequence of addresses that represents interleaving instruction (α(i)). During the interleaving mode involving a reading process and during the deinterleaving mode involving a writing process, a logical means (XOR, MUX) causes the data memory (RAM) to be addressed by the second address generator (AG).