The present invention relates to a CAS latency control circuit of SDRAM (Synchronous DRAM) for improving the speed of the first and second CAS latency operations, wherein the first and second signals are inputted by inputting a clock signal (QCLK) signal that controls data output. And a control circuit unit for outputting third and fourth control signals, first latch means for passing or latching data from within according to the first control signal of the control circuit unit, and a second control signal of the control circuit unit. According to the second latch means for passing or latching the data output from the first latch means, and directly outputting data from the inside according to the fourth control signal of the control circuit part or outputted from the second latch means. A data path selector for outputting data and data output from the data path selector according to a third control signal of the control circuit part to the data output buffer; It is configured including the third latch means and the latch.
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