Semiconductor memory device using dedicated command and address strobe signal and method for inputting command and address thereof

摘要

Synchronous DRAM reduces latency by the time difference between the arrival of commands and addresses and the arrival time of the system clock, and also enables the safe transfer of commands and addresses to all synchronous DRAMs within one clock cycle time even if the frequency of the system clock is increased. And a command and address input method thereof. The synchronous DRAM operating according to the command and address input method receives a command and address only strobe signal, which is a signal different from the system clock, to strobe a command and an address. The command and address only strobe signal is a signal that is only active during the period in which the command and address are input to the synchronous DRAM or is a free running clock that continuously toggles. Therefore, it is possible to safely transfer commands and addresses to all synchronous DRAMs of a memory module regardless of the frequency of the system clock. In addition, even if the frequency of the system clock is increased, since the commands and addresses are correctly input in response to the command and address-specific strobe signal independent of the system clock, the latency of the time between the arrival time of the commands and addresses and the arrival time of the system clock is reduced. There is an advantage.