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Finite field multiplier having improved structure of linear feedback shift register
Finite field multiplier having improved structure of linear feedback shift register
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机译:具有改进的线性反馈移位寄存器结构的有限域乘法器
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摘要
PURPOSE: A finite field adder of an improved linear loop feedback shift register structure is provided to increase a process speed without increasing the number of registers. CONSTITUTION: The first input cells(ACELL0-ACELL(m/2)-1) shift at least two first input data by responding to one clock signal while shifting the first input data. The second input cells(BCELL0-BCELL(m/2)-1) shift at least two second input data by responding to one clock signal while shifting the second input data. Output registers(Z0-Zm-1) store the result data according to an output value from the first and the second input cells. The clock signal, inputted to the first and the second input cells, is the same clock signal.
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