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Pipeline-type microprocessor that prevents the cache from being read if the contents of the cache are invalid
Pipeline-type microprocessor that prevents the cache from being read if the contents of the cache are invalid
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机译:流水线型微处理器,如果高速缓存的内容无效,则防止读取高速缓存
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摘要
When a cache is read, the power consumed by cache memory is reduced by using cache access circuitry to prevent the cache from being read, in which case the information stored in the cache is powered by the processor by the user. And valueless or invalidation bits, such as when reset, are set.
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