Fault-tolerant architecture data processing system with direct replacement cell

摘要

The cell contains a monolithic network of cells with sufficient margin provided through direct logical replacement of the defective cell by the spare cell to allow large monolithic cell arrangements without unacceptable defects being organized. A data processing system is provided. The data processing system according to the present invention has a chip-size limit and an off-chip connection bottleneck of chip-base architecture, a von Neumann bottleneck of uniprocessor architecture, memory and I / 0 bottleneck of parallel processing architecture, It overcomes the input bandwidth bottlenecks of high-resolution display and supports integration into a single entity with a massive parallel data processing system.