Detection and compensation circuit for bit-slip-errors during transmission of digital data is installed in receiver and transmitter produces equal-width bit sequences with identification markings

摘要

The switching system allows a maximum of two bit-slip errors and uses identification or marking bit sequences with a length of 5 bits. Each message sequence (1) is preceded by two buffer bits (3) and is followed by a marker sequence (2). The buffer and message bits pass to a multiplexer (6) which produces a single output. The system includes an input register (4) and an addressing device (5). The addressing device contains 5 comparators (8-8'''') receiving different combinations of marker bits, and a different test signal. If the test and received signals are identical, a signal is produced, e.g. 'bit-slip-left-2'. The bit-slip signal is passed to a selector-generator (7), which produces an address output for the multiplexer.