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Power semiconductor switch turn-off performance optimization method, by dropping gate-emitter voltage e.g. of IGBT in two stages

机译:通过降低栅极发射极电压(例如)降低功率半导体开关的关断性能优化方法IGBT分为两个阶段

摘要

When a switch-off signal arrives, the gate-emitter voltage (UGE) of the power semiconductor switch (IGBT) is dropped in two stages. Firstly, the gate-emitter voltage is dropped to a level (U2) which causes a collector-emitter forward voltage that is increased by a predetermined value. Then, the gate-emitter voltage is dropped to the final switch-off value (U3). Independent claims are also included for: (1) an apparatus for carrying out the method; (2) a hard-switching power converter.
机译:当关闭信号到达时,功率半导体开关(IGBT)的栅极-发射极电压(UGE)分两级下降。首先,栅极-发射极电压下降到电平(U2),该电平导致集电极-发射极正向电压增加预定值。然后,栅极-发射极电压下降到最终关断值(U3)。还包括以下独立权利要求:(1)一种用于执行该方法的设备; (2)硬开关电源转换器。

著录项

  • 公开/公告号DE10206392A1

    专利类型

  • 公开/公告日2003-09-04

    原文格式PDF

  • 申请/专利权人 SIEMENS AG;

    申请/专利号DE2002106392

  • 申请日2002-02-15

  • 分类号H03K17/042;H03K17/0412;H03K17/567;H03K17/082;H03K17/0812;

  • 国家 DE

  • 入库时间 2022-08-21 23:42:15

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