Improved neuronal half conductor chip architectures and neuronal network therein works

摘要

There is disclosed the architecture of a neural semiconductor chip (10) first including a neuron unit (11(#)) comprised of a plurality of neuron circuits (11-1, ...) fed by different buses transporting data such as the input vector data, set-up parameters, ... and control signals. Each neuron circuit (11) includes means for generating local result (F, ... ) signals of the "fire" type and a local output signal (NOUT) of the distance or category type on respective buses (NR-BUS, NOUT-BUS). An OR circuit (12) performs an OR function for all corresponding local result and output signals to generate respective first global result (R*) and output (OUT*) signals on respective buses (R*-BUS, OUT*-BUS) that are merged in an on-chip common communication bus (COM*-BUS) shared by all neuron circuits of the chip. An additional OR function is then performed between all corresponding first global result and output signals to generate second global result (R**) and output (OUT**) signals, preferably by dotting on an off-chip common communication bus (COM**-BUS) in the driver block (19). This latter bus is shared by all the neural chips that are connected thereon to incorporate a neural network of the desired size. In the chip, a multiplexer (21) may select either the first or second global output signal to be reinjected in all neuron circuits of the neural network as a feed-back signal depending on the chip operates in a single or multi-chip environment via a feed-back bus (OR-BUS). The feedback signal results of a collective processing of all the local signal. MATH