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Detection technique of memory section errors and individual -, double and triple bit errors

机译:内存段错误以及单个,双位和三位错误的检测技术

摘要

The bits of a data block are logically partitioned into an array that includes a number of columns equal to a number of memory devices and a number of rows equal to a number of bits of the data block stored in each memory device. Each memory device contributes one bit to each row. In one embodiment, the bits from a memory device are stored in the same column position of all the rows. One check bit is associated with each row. The check bit is computed by taking the parity of the row associated with the check bit and zero or one column. Each column is assigned to at least four check bits. If a check bit has a column assigned to it, then the check bit is generated by computing the parity of the associated row and the column assigned to the check bit. Alternatively, if the check bit does not have a column assigned to it, the check bit is generated by computing the parity of the row assigned to the check bit only. Each column is assigned to at least four check bits and is assigned to an even number of check bits.
机译:数据块的位在逻辑上划分为一个数组,该数组包括等于存储设备数量的列数和等于每个存储设备中存储的数据块的位数的行数。每个存储设备为每一行贡献一位。在一个实施例中,来自存储设备的位被存储在所有行的相同列位置中。每行关联一个校验位。通过获取与校验位和零或一列关联的行的奇偶校验来计算校验位。每列至少分配给四个校验位。如果校验位具有分配给它的列,则通过计算关联行和分配给校验位的列的奇偶校验来生成校验位。可替换地,如果校验位没有分配给它的列,则通过仅计算分配给校验位的行的奇偶校验来生成校验位。每列至少分配给四个校验位,并且分配给偶数个校验位。

著录项

  • 公开/公告号DE69904618T2

    专利类型

  • 公开/公告日2003-09-18

    原文格式PDF

  • 申请/专利权人 SUN MICROSYSTEMS INC.;

    申请/专利号DE1999604618T

  • 发明设计人 CYPHER ROBERT;

    申请日1999-09-22

  • 分类号G06F11/10;

  • 国家 DE

  • 入库时间 2022-08-21 23:38:30

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