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Method and device for the recovery of synchronization clock by symbols from a signal possessing great possibilities in frequency

机译:通过符号从具有很大频率可能性的信号中恢复同步时钟的方法和装置

摘要

Device for the clock recovery of synchronization symbols on the basis of a reception signal having a wide range of error or offset in frequency. The amplitudes of signals in phase and quadrature sampled is determined (210). These amplitudes are added and (227) in the registers to the accumulator (231, 233, 235, 237, 239) to the sum of the sums of the first and second signals for each sampling time and practically over the length of a pulse in the waiting. A circuit for determining the maximum / minimum (240) chosen, the sampling time having a greater or smaller amount to provide a recovered clock signal (270). The carrier can then be recovered (260) and a sampler downwards (250) sampled at the bottom of the reception signals in phase and quadrature on the basis of the recovered clock signal.
机译:用于基于具有宽范围的误差或频率偏移的接收信号对同步符号进行时钟恢复的设备。确定在相位和正交采样的信号的幅度(210)。将这些振幅相加并在寄存器中将(227)累加到累加器(231、233、235、237、239)中,以得到每个采样时间的第一信号和第二信号之和的总和,实际上是在脉冲长度内等待中。用于确定所选择的最大/最小值的电路(240),采样时间具有更大或更小的量以提供恢复的时钟信号(270)。然后可以恢复载波(260),并根据恢复的时钟信号在相位和正交的接收信号的底部向下采样(250)采样器。

著录项

  • 公开/公告号FR2734107B1

    专利类型

  • 公开/公告日2002-11-29

    原文格式PDF

  • 申请/专利权人 MOTOROLA INC;

    申请/专利号FR19960005535

  • 申请日1996-05-03

  • 分类号H04B7/212;H04L12/43;

  • 国家 FR

  • 入库时间 2022-08-21 23:38:15

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