A compact turbo-decoder having high efficiency, comprises two sets of processors for computing in parallel the syndromes and for updating in parallel the block, respectively

摘要

The method for decoding the data encoded by blocks by use of a turbo-code comprises the steps of implementing different algorithms so that at least two steps are suited for applying in parallel to different blocks of data. The steps comprise a first step for computing a syndrome and a second step for updating the block by use of the syndrome computed in the course of the first step. The first step is carried out on a first part of the first block, and the second step is carried out on a second part of the first block or a part of the second block. In the first step a set of n first processors (PROC1) is operated in parallel on n rows, respectively columns, of a block, and in the second step a set of m second processors (PROC2) is operated in parallel on m rows, respectively columns, of a block. A block of data is of dimension 32 x 32 and n = m = 16. The data are coded by a coding of type BCH or extended BCH, and the updating is by use of an algorithm of Berlekamp or Euclide followed by an algorithm of Chase-Pyndiah. The decoding circuit (20) is claimed and comprises the first set of processors (PROC1) for computing the syndromes in parallel, where each syndrome corresponds to a syndrome of a row, respectively column, of the first part of the first block of data, and the second set of processors (PROC2) for updating in parallel the rows, respectively columns, of the second part of the first block or a part of the second block of data. The decoding circuit also comprises a first group of memory stores (A) which includes the random-access memories (RAM1,RAM1',RAM1'',RAM1''') including two optional (RAM10,RAM10') with access along rows, which can store at least two successive blocks of data, a second group of memory stores (B) including the random-access memories (RAM12,RAM13) as the working memory, a fourth group of memory stores (D) including the random-access memories (RAM14,RAM15) as the working memory or the buffer memory, a random-access memory (RAM18) for storing a block after processing and an optional FORMAT module connected to output (OUT'), a processing block 922) at input (IN') with a depuncturing module (DEPUNC), a bus (25), and a controller (27). Each memory store has a direct access to the bus. The decoding circuit allows to carry out 4 consecutive iterations in real time for the data flow rate of up to 54 Mbit/s and the blocks of dimension 32x32.