PROCESSOR SYSTEM, INSTRUCTION STRING OPTIMIZATION DEVICE AND INSTRUCTION STRING OPTIMIZATION PROGRAM

摘要

PPROBLEM TO BE SOLVED: To reduce the power consumption of a processor system having a plurality of processors without lowering the throughput thereof. PSOLUTION: A flag detection part 101 detects an assignment control flag and a clock control flag both added to an instruction code. An instruction assignment control part 102 outputs the instruction code to a CPU 103 or an HWE 104 which is based on the detection and makes it execute the instruction code. On the basis of the detection, a clock control part 106 reduces the power consumption by supplying a clock signal of a frequency lower than a maximum clock frequency to the CPU 103 or the HWE 104 that involve latency if operated at the maximum clock frequency. PCOPYRIGHT: (C)2004,JPO&NCIPI