Method and apparatus to be connected to the memory array large parallel processor array by a technique sequentially bit

摘要

A method and apparatus for connecting to the memory the processor array of MPP array, data conversion by the software and not required, method and apparatus in which data is stored directly in the memory by the mode of either the vertical mode or normal mode But it is disclosed. Circuit connection is provided by a large number of PE to share their connection to a plurality of data bits in the memory array. Each PE stores the data (or written) in relation to a memory buffer a plurality of registers, read from the memory data bits of one or two. Horizontal The (normal) mode connection is selected all the bits of one byte is given to be stored in the same PE, that is, each set of buffer registers associated with the PE to the corresponding memory bit by an external device encompasses one byte to be handled. In vertical (bit serial) mode, each set of buffer register includes the position of the sequential memory corresponding to the position of the PE of the memory word bits sequentially. The selection is made by utilizing the tri-state driver set for operating the data lines and the multiplexer as an input to the register.