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Hard macro test circuit, the test methods and test pattern generation method

机译:硬宏测试电路,测试方法和测试图案生成方法

摘要

PROBLEM TO BE SOLVED: To provide circuit constitution capable of testing integrally both signal body inspection for a hard macro circuit and inspection for a peripheral circuit in the hard macro, as scan path inspection for a circuit including the hard macro.;SOLUTION: A scan pattern for the macro wherein logics in combinational circuits 21, 22 are taken into account is set in a scan flip-flop SCAN-FF 30 on the input side from a scan-in terminal SIN, an output of the SCAN-FF 30 is input to the hard macro circuit 2 via the combinational circuit 21 on the input side, an operated result in the circuit 2 is taken into the SCAN-FF 30 on the output side via the combinational circuit 22 on the output side, and the output of the SCAN-FF 30 is output as a comparision signal for comparing it with an expected value preliminarily set in a scan output terminal SOT.;COPYRIGHT: (C)2001,JPO
机译:解决的问题:提供一种电路结构,该结构能够对硬宏电路的信号体检查和硬宏中的外围电路进行整体测试,作为包括硬宏的电路的扫描路径检查。在从扫描输入端子SIN起的输入侧的扫描触发器SCAN-FF 30中设置考虑了组合电路21、22的逻辑的宏的模式,输入SCAN-FF 30的输出经由输入侧的组合电路21到硬宏电路2,电路2中的运算结果经由输出侧的组合电路22进入输出侧的SCAN-FF 30,并且输出的组合SCAN-FF 30作为比较信号输出,用于与扫描输出端子SOT中预先设置的期望值进行比较。; COPYRIGHT:(C)2001,JPO

著录项

  • 公开/公告号JP3544912B2

    专利类型

  • 公开/公告日2004-07-21

    原文格式PDF

  • 申请/专利权人 NECマイクロシステム株式会社;

    申请/专利号JP20000020411

  • 发明设计人 高須賀 志丞;

    申请日2000-01-28

  • 分类号G01R31/28;G01R31/3183;

  • 国家 JP

  • 入库时间 2022-08-21 23:25:56

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