Bus bridge including a memory controller having a memory request arbitration mechanism was improved

摘要

A memory controller having a memory request arbitration mechanism was improved bus bridge including (210) (102) is disclosed. Memory controller (210), subject to a variety of requests to be written to the (104) main memory read or liked by (104) main memory. In one particular embodiment, the memory controller (210), a page hit request, a page miss bank request, a page miss, the incoming requests are - have been arranged to classify the page conflict request and another chip select request, it may be. A memory controller (210) may be configured to prioritize based on the waiting time these requests. Arbitration priority higher than the page miss bank request page hit requests, page miss page miss bank request - arbitration higher priority than another chip select request, page miss - another chip select request arbitration than the page conflict request Priority is high. In order to service requests based on the priority (210) to enhance the utilization of the memory bus and SDRAM bus (106) the memory controller.