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Circuit arrangement for quantizing digital signals and filtering quantization noise

机译:用于量化数字信号和滤波量化噪声的电路装置

摘要

The invention relates to a circuit configuration for quantization of digital signals and for filtering quantization noise. Said circuit configuration comprises a multitude of digital control loops connected in series and having quantizers. The digital signals having a word length of m-bits are fed to a first control loop in the series. The quantization error signal of each quantizer is filtered and fed back to the corresponding digital control loop. It is then fed to a downstream digital control loop. The quantized output signal of the first digital control loop is adapted to a third word length of u-bits which is smaller than the first word length. Except for the quantized output signal of the first digital control loop, the quantized output signals of the digital control loops of the series are respectively filtered by a digital filter. In an adder, said quantized output signals are then added to the first quantized output signal of the first digital control loop of the series to prevent quantization errors. The output signal of the adder has a second word length of n-bits and represents the quantized output signal of the circuit configuration.
机译:本发明涉及一种用于数字信号量化和用于滤波量化噪声的电路配置。所述电路配置包括串联连接并具有量化器的多个数字控制回路。具有m位的字长的数字信号被馈送到该系列中的第一控制回路。每个量化器的量化误差信号被滤波并反馈到相应的数字控制回路。然后将其馈送到下游数字控制回路。第一数字控制环路的量化输出信号适合于u位的第三字长,该字长小于第一字长。除了第一数字控制回路的量化输出信号之外,该系列的数字控制回路的量化输出信号分别由数字滤波器滤波。然后在加法器中,将所述量化的输出信号加到该系列的第一数字控制回路的第一量化的输出信号上,以防止量化误差。加法器的输出信号具有n位的第二字长,并且表示电路配置的量化输出信号。

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