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Butterfly-processing element for efficient fast fourier transform method and apparatus

机译:高效快速傅立叶变换的蝴蝶处理元件和装置

摘要

A Fast Fourier Transformation (FFT) method and apparatus is implemented using a radix-r butterfly design based on a reduced single phase of calculation, termed a butterfly-processing element (BPE). Butterfly calculations are each executed in the same number of iterations, and comprised of substantially identical butterfly-processing elements. The resulting algorithm, in which a number of parallel processors operate simultaneously by a single instruction sequence, reduces both the computational burden and the communication burden. The use of substantially identical butterfly-processing elements, repeated in combination to form a radix-r butterfly, enables the design of FFT butterflies containing identical structures and a systematic means of accessing the corresponding multiplier coefficients stored in memory. The butterfly-processing element substantially reduces the complexity of the radix-r butterfly, particularly for higher order radices. In particular, starting from the basic DFT equations, the adder matrix is factored and combined with the twiddle matrix to form a single phase of calculation. By grouping all the multiply calculations into one calculation phase and all the addition calculations into the remaining calculation phases, the total number of calculations is reduced and the degree of parallelism is increased. Trivial multiplications, encountered during the execution of particular butterflies, are avoided by simple checks on the coefficient addresses. An efficient address generator is provided to access or store the twiddle factors, the input data and the output data.
机译:快速傅立叶变换(FFT)方法和装置使用基于减少的单相计算的基数r蝶形设计实现,称为蝶形处理元素(BPE)。蝶形计算每个都以相同的迭代次数执行,并且由基本相同的蝶形处理元素组成。由此产生的算法(其中多个并行处理器按单个指令序列同时运行)减少了计算负担和通信负担。通过使用基本相同的蝶形处理元素(组合重复以形成基数r形蝶形),可以设计包含相同结构的FFT蝶形,以及访问存储在存储器中的相应乘数系数的系统方法。蝶形处理元件显着降低了基数r蝶形的复杂性,尤其是对于高阶半径而言。特别是,从基本DFT方程开始,将加法器矩阵分解并与旋转矩阵合并,以形成一个单相计算。通过将所有乘法计算分组为一个计算阶段,并将所有加法计算分组为其余的计算阶段,可减少计算总数,并提高并行度。通过对系数地址的简单检查,可以避免执行特定蝶形时遇到的琐碎乘法。提供了一个有效的地址生成器来访问或存储旋转因子,输入数据和输出数据。

著录项

  • 公开/公告号US6751643B2

    专利类型

  • 公开/公告日2004-06-15

    原文格式PDF

  • 申请/专利权人 JABER ASSOCIATES LLC;

    申请/专利号US20010768812

  • 发明设计人 MARWAN A JABER;

    申请日2001-01-24

  • 分类号G06F171/40;

  • 国家 US

  • 入库时间 2022-08-21 23:18:37

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