首页> 外国专利> DELAY LOCKED LOOP DESIGN WITH DIODE FOR LOOP FILTER CAPACITANCE LEAKAGE CURRENT CONTROL

DELAY LOCKED LOOP DESIGN WITH DIODE FOR LOOP FILTER CAPACITANCE LEAKAGE CURRENT CONTROL

机译:带二极管的延时锁定环设计,用于环滤波器电容泄漏电流控制

摘要

A delay locked loop design that uses a diode operatively connected to a loop filter capacitor to control a leakage current of the loop filter capacitor is provided. By positioning a diode in series with the loop filter capacitor, a voltage potential across the loop filter capacitor is reduced, thereby reducing the leakage current of the loop filter capacitor. Moreover, the leakage current of the loop filter capacitor is controlled in that it cannot exceed the current through the diode. Control and reduction of the loop filter capacitor leakage current leads to more reliable and stable delay locked loop behavior.
机译:提供了一种延迟锁定环路设计,其使用可操作地连接到环路滤波电容器的二极管来控制环路滤波电容器的泄漏电流。通过将二极管与环路滤波电容器串联放置,降低了环路滤波电容器两端的电压电势,从而减小了环路滤波电容器的泄漏电流。此外,控制环路滤波电容器的泄漏电流,使其不能超过通过二极管的电流。控制和减小环路滤波电容器的漏电流会导致更可靠,更稳定的延迟锁定环路行为。

著录项

相似文献

  • 专利
  • 外文文献
  • 中文文献
获取专利

客服邮箱:kefu@zhangqiaokeyan.com

京公网安备:11010802029741号 ICP备案号:京ICP备15016152号-6 六维联合信息科技 (北京) 有限公司©版权所有
  • 客服微信

  • 服务号