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Method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design
Method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design
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机译:避免在集成电路设计的缺陷分析过程中由于虚假互连而引起的错误故障的方法
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摘要
A method for avoiding false failures attributable to dummy interconnects during defect analysis of an integrated circuit design is described. Described processing includes retrieving conductivity layers information for an integrated circuit design from a GDSII formatted file; defining a dummy polygons layer and a target layer; restoring interconnect polygons from the conductivity layers information into the dummy polygons layer; copying the interconnect polygons from the dummy polygons layer to the target layer, except for dummy interconnect polygons; and performing defect analysis of the integrated circuit design using the target layer.
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