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Circuit for merging and aligning prepend data and payload data
Circuit for merging and aligning prepend data and payload data
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机译:合并和对齐前置数据和有效载荷数据的电路
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摘要
A circuit that merges and aligns data that resides in a buffer entry is described. The data residing in the buffer entry is divided into a prepend portion and a payload portion. The prepend and the payload portions of the data are each defined, in part, by a length and an offset. Given the lengths and offsets, the circuit fetches the data from the buffer entry, merges the data, and aligns the data.
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