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Adaptive variable frequency clock system for high performance low power microprocessors
Adaptive variable frequency clock system for high performance low power microprocessors
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机译:高性能低功耗微处理器的自适应可变时钟系统
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摘要
A method for dynamically varying a clock frequency in a processor. The method of one embodiment comprises driving a clock distribution network with a clock output from a phased locked loop (PLL). An adjustable clock generator is locked with the phased locked loop. The adjustable clock generator is substituted for the PLL on the clock distribution network.
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