TECHNIQUE FOR OPTIMIZING DECOUPLING CAPACITANCE SUBJECT TO LEAKAGE POWER CONSTRAINTS

摘要

A technique for optimizing decoupling capacitance on an integrated circuit while meeting leakage power constraints of the integrated circuit is provided. The technique involves the formulation of a linear optimization problem using physical characteristics and constraints of the integrated circuit, where a linear solution to the linear optimization problem yields an optimal decoupling capacitance presence on the integrated circuit.