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Method and apparatus for automatically generating hardware from algorithms described in matlab
Method and apparatus for automatically generating hardware from algorithms described in matlab
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机译:根据Matlab中描述的算法自动生成硬件的方法和设备
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摘要
Digital circuit is synthesized from algorithm described in the MATLAB programming language. A MATLAB program is compiled into RTL-VHDL, which is synthesizable using system-specific tools to develop ASIC or FPGA configuration. Intermediate transformations and optimizations are performed to obtain highly optimized description in RTL-VHDL or RTL Verilog of given MATLAB program. Optimizations include levelization, scalarization, pipelining, type-shape analysis, memory optimizations, precision analysis and scheduling.
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