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Multi-tiered memory bank having different data buffer sizes with a programmable bank select
Multi-tiered memory bank having different data buffer sizes with a programmable bank select
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机译:具有不同数据缓冲区大小且具有可编程存储体选择的多层存储体
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摘要
An apparatus having a core processor and a plurality of cache memory banks is disclosed. The cache memory banks are connected to the core processor in such a way as to provide substantially simultaneous data accesses for said core processor.
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