Method and apparatus to assemble data segments into full packets for efficient packet-based classification

摘要

Processor architectures, and in particular, processor architectures that assemble data segments into full packets for efficient packet-based classification. In accordance with an embodiment of the present invention, a method for assembling received data segments into full packets in an initial processing stage in a processor includes receiving a plurality of data segments from a packet, determining a first storage location for each of the plurality of data segments, and storing each of the plurality of data segments in its determined first storage location. The method also includes determining a second storage location for each of the plurality of data segments, said second storage locations being logically ordered to represent the order the data segments originally occurred in the packet and storing each of the plurality of data segments in its determined second storage location to re-assemble the packet. The method further includes releasing the first storage location associated with each data segment after storing the data segment in its determined second storage location and, upon the storing of an end of packet data segment from the packet in its determined second storage location, passing control of the plurality of related data segments to a next processing stage in the processor.