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Method, system and program product comprising breakpoint handling mechanism for debugging and/or monitoring a computer instruction sequence

机译:包括用于调试和/或监视计算机指令序列的断点处理机制的方法,系统和程序产品

摘要

A computer method, system and program product for debugging and/or monitoring an instruction set and having an improved breakpoint handling mechanism involving a hardware debug register set (or like breakpoint register means). Instead of patching a break instruction into a debuggee instruction sequence, re-inserting the original instruction and then single stepping through that instruction before replacing it with the patch, the original instruction is left in place and continuous execution is resumed. Before resuming however, the breakpoint register is set so that the break instruction can be re-applied while a flag (eg the Intel RF flag) is set so as to prevent a hardware break before that is desired.
机译:一种用于调试和/或监视指令集并具有涉及硬件调试寄存器集(或类似的断点寄存器装置)的改进的断点处理机制的计算机方法,系统和程序产品。无需将中断指令修补到被调试对象指令序列中,而是重新插入原始指令,然后在逐步替换该修补程序之前单步执行该指令,而将原始指令保留在原处,并继续执行连续指令。但是,在恢复之前,设置断点寄存器,以便在设置标志(例如Intel RF标志)时可以重新应用break指令,以防止在需要之前发生硬件中断。

著录项

  • 公开/公告号US6708326B1

    专利类型

  • 公开/公告日2004-03-16

    原文格式PDF

  • 申请/专利权人 INTERNATIONAL BUSINESS MACHINES CORPORATION;

    申请/专利号US20000710164

  • 发明设计人 SUPARNA BHATTACARYA;

    申请日2000-11-10

  • 分类号G06F94/40;G06F110/00;G06F150/00;

  • 国家 US

  • 入库时间 2022-08-21 23:14:12

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