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Realtime parallel processor system for transferring common information among parallel processors to a cache memory system
Realtime parallel processor system for transferring common information among parallel processors to a cache memory system
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机译:实时并行处理器系统,用于将并行处理器之间的公共信息传输到缓存系统
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摘要
A CPU system having a built-in cache memory system in which a write-only port for coherence control from the common system side and an access port from the CPU side are isolated through a multi-port configuration of the cache memory system inside CPU. A common memory on the common side too, uses a 2-port system structure with the CPU system in the form of a broadcast type connection form.
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