Framework for multiple-engine based verification tools for integrated circuits

摘要

A design verification system comprising a set of modular verification engines invoked by a framework that manages the control flow between the engines. The framework receives a verification problem from an application and attempts to solve it by instantiating one or more engine in a customizable sequence or set of sequences. Each verification engine is configured to achieve a specific verification objective and may be coded against a common API to facilitate exchange of information between the engines. The verification engines may include reduction engines, which attempt to simplify a problem by modifying it or decomposing it, and decision engines, which attempt to solve problems that are passed to them. As a verification problem is passed from one engine to the next, the engine may alter the verification problem such that a decision engine at the end of the sequence may receive a verification problem that is simpler to solve than the original problem specified by the system user. If the decision engine is able to solve a problem by determining a state or sequence of states that produces a specified value on a specified node of the design, the engine passes the determined sequence to the engine that invoked it in the form of a counterexample trace after modifying it to undo whatever effect it may have had on the problem. The engines may also learn facts, such as a lighthouse that serves as an aid to solving the verification problem, and pass these facts to the other engines.